The present invention relates to a semiconductor device and a process for the fabrication thereof, particularly a structure and a fabrication process of a semiconductor device capable of preventing the resistance of a wiring from increasing due to oxidation of the wiring which contains copper.
The development of LSI which enables to create an economical and high-performance system permitting the very high speed processing of large-capacity signals has been accelerated. Upon development, there is a demand for reducing a delay in the wirings formed in the LSI.
With a view to satisfying the above demand, copper (Cu) or copper alloy is being employed as a metal having a low resistance and high migration resistance. Since Cu is a metal of low resistance compared with conventionally used Al, it seems to be a material which can attain the reduction of an interconnection delay. It however requires an anti-oxidation film to prevent oxidation of the surface of a copper (Cu) wiring because the copper is oxidized faster than aluminum (Al). Examples of the material for an anti-oxidation layer include transition metals such as Nb, Ta, Cr, Mo and W; metals such as Mg and Al; and nitride films such as TiWN and SiN/NSG. It has been proposed various methods of depositing such a material as an anti-oxidation layer at the periphery of the copper wiring, for example, Unexamined Japanese Patent Publication 3-152807; Appl. Phys. Lett., 63, 934(1993); Unexamined Japanese Patent Publication 3-196619 or 3-196620.
A description will next be made of conventional processes for the formation of an anti-oxidation layer with reference to accompanying drawings.
First, it is described a process for forming a copper wiring using an anti-oxidation layer as show in Unexamined Japanese Patent Publication 3-152807. FIGS. 4(a) to 4(d) are cross-sectional views in this forming process of the copper wiring.
In FIG. 4(a), an SiO.sub.2 layer as an insulating layer 2 and an intermediate insulating layer 3 are stacked successively on a semiconductor substrate 1, followed by patterning the intermediate insulating layer 3 by the photolithography, whereby an opening portion is formed in a region in which a copper wiring is to be formed. The anti-oxidation layer 4 is then formed selectively on the opening portion. As illustrated in FIG. 4(b), a copper wiring 9 is deposited so as to cover the opening portion sufficiently. Examples of the deposition method include sputtering method and CVD method. As illustrated in FIG. 4(c), an unnecessary portion of copper is removed until the intermediate insulating layer 3 is exposed. Finally, an anti-oxidation layer is formed again on the exposed copper as illustrated in FIG. 4(d).
Next, it is described a process for forming a copper wiring using an anti-oxidation layer as show in Appl. Phys. Lett., 63, 934(1993). FIGS. 5(a) to 5(d) are cross-sectional views in this forming process of the copper wiring.
In FIG. 5(a), an SiO.sub.2 layer as an insulating layer 2 and an intermediate insulating layer 3 are stacked successively on a semiconductor substrate 1, followed by patterning the intermediate insulating layer 3 by the photolithographic technique, whereby an opening portion is formed in a region in which a copper wiring is to be formed. The anti-oxidation layer 4 (mainly a transition metal such as Nb, Ta, Cr, Mo or W) is then formed selectively in the opening portion. As illustrated in FIG. 5(b), a copper wiring 9 is deposited so as to cover the opening portion sufficiently. Examples of the deposition method include sputtering method and CVD method. As illustrated in FIG. 5(c), an unnecessary portion of copper is removed until the intermediate insulating layer 3 is exposed. Finally, as illustrated in FIG. 5(d), self-passivation is formed by diffusing the metal for the underground anti-oxidation layer on the Cu surface by thermal treatment.
Further, it is described a process for forming a copper wiring using an anti-oxidation layer as show in Unexamined Japanese Patent Publication 3-196619 or 3-196620. FIGS. 6(a) to 6(c) are cross-sectional views in this forming process of the copper wiring.
In FIG. 6(a), an SiO.sub.2 layer as an insulating layer 2 and an intermediate insulating layer 3 are stacked successively on a semiconductor substrate 1, followed by patterning the intermediate insulating layer 3 by the photolithographic technique, whereby an opening portion is formed in a region in which a copper wiring is to be formed. A copper wiring 9 is then deposited so as to cover the opening portion sufficiently. At this time, an element (Nb, Ta, Cr, Mo or W or a metal such as Mg or Al) which is to be an anti-oxidation layer together with copper is added to copper in advance. Examples of the deposition method include sputtering method and CVD method. As illustrated in FIG. 6(b), an unnecessary portion of copper is then removed until the intermediate insulating layer 3 is exposed. Finally, as illustrated in FIG. 6(c), self-passivation is formed by diffusing the metal for the underground anti-oxidation layer on the Cu surface by thermal treatment.
However, the above-described conventional processes for the formation of a copper wiring however are not free from the problems as described below.
Described specifically, in the above-described process for the formation of an anti-oxidation layer for Cu, the vacuum treatment is employed for the formation of the anti-oxidation layer and copper layer, but it is low in through-put. In addition, it is necessary to form both the anti-oxidation layer and copper as a wiring material by the treatment in the vacuum, which requires the use of respective film forming apparatuses.
Moreover, when an anti-oxidation layer is formed by diffusion caused by thermal treatment, the temperature is as high as about 700.degree. C. At this time the grain size of copper, which is a material for a wiring, becomes large, resulting in a change in the resistance value of the wiring.